1. Field of the Invention
The present disclosure generally relates to the fabrication of integrated circuits, and, more particularly, to various methods of forming reduced resistance local interconnect structures and the resulting semiconductor devices.
2. Description of the Related Art
In modern integrated circuits, such as microprocessors, storage devices and the like, a very large number of circuit elements, especially transistors, are provided and operated on a restricted chip area Immense progress has been made over recent decades with respect to increased performance and reduced feature sizes of circuit elements, such as transistors. However, the ongoing demand for enhanced functionality of electronic devices forces semiconductor manufacturers to steadily reduce the dimensions of the circuit elements and to increase the operating speed of the circuit elements. The continuing scaling of feature sizes, however, involves great efforts in redesigning process techniques and developing new process strategies and tools so as to comply with new design rules. Generally, in complex circuitry including complex logic portions, MOS technology is presently a preferred manufacturing technique in view of device performance and/or power consumption and/or cost efficiency. In integrated circuits fabricated using MOS technology, field effect transistors (FETs), such as planar field effect transistors and/or FinFET transistors, are provided that are typically operated in a switched mode, i.e., these transistor devices exhibit a highly conductive state (on-state) and a high impedance state (off-state). The state of the field effect transistor is controlled by a gate electrode, which controls, upon application of an appropriate control voltage, the conductivity of a channel region formed between a drain region and a source region.
To improve the operating speed of FETs, and to increase the density of FETs on an integrated circuit device, device designers have greatly reduced the physical size of FETs over the years. More specifically, the channel length of FETs has been significantly decreased, which has resulted in improving the switching speed of FETs. However, decreasing the channel length of a FET also decreases the distance between the source region and the drain region. In general, as a result of the reduced dimensions of the transistor devices, the operating speed of the circuit components has been increased with every new device generation, and the “packing density,” i.e., the number of transistor devices per unit area, in such products has also increased during that time. Such improvements in the performance of transistor devices has reached the point where one limiting factor relating to the operating speed of the final integrated circuit product is no longer the individual transistor element but the electrical performance of the complex wiring system that is formed above the device level that includes the actual semiconductor-based circuit elements.
Typically, due to the large number of circuit elements and the required complex layout of modern integrated circuits, the electrical connections of the individual circuit elements cannot be established within the same device level on which the circuit elements are manufactured, but require one or more additional metallization layers, which generally include metal-containing lines providing the intra-level electrical connection, and also include a plurality of inter-level connections or vertical connections, which are also referred to as vias. These vertical interconnect structures comprise an appropriate metal and provide the electrical connection of the various stacked metallization layers.
Furthermore, in order to actually connect the circuit elements formed in the semiconductor material with the metallization layers, an appropriate vertical contact structure is provided, a first lower end of which is connected to a respective contact region of a circuit element, such as a gate electrode and/or the drain and source regions of transistors, and a second end is connected to a respective metal line in the metallization layer by a conductive via. Such vertical contact structures are considered to be “device-level” contacts or simply “contacts” within the industry, as they contact the “device” that is formed in the silicon substrate. The contact structures may comprise contact elements or contact plugs having a generally square-like or round shape that are formed in an interlayer dielectric material, which in turn encloses and passivates the circuit elements. In other applications, the contact structures may be line-type features, e.g., source/drain contact structures.
In some cases, the second, upper end of the contact structure may be connected to a contact region of another semiconductor-based circuit element, in which case the interconnect structure in the contact level is also referred to as a local interconnect. These local interconnect structures typically connect circuit elements, e.g., transistors, resistors, etc., that are formed on different spaced-apart active regions that are electrically isolated from one another. Such local interconnect structures are generally line-type structures that are formed in the interlayer dielectric material below the metallization system of the product.
As the critical dimensions of the circuit elements in the device level decreased, the dimensions of metal lines, vias and contact elements were also reduced. In some cases, the increased packing density mandated the use of sophisticated metal-containing materials and dielectric materials in order to reduce the parasitic capacitance in the metallization layers and provide a sufficiently high conductivity of the individual metal lines and vias. For example, in complex metallization systems, copper in combination with low-k dielectric materials, which are to be understood as dielectric materials having a dielectric constant of approximately 3.0 or less, are typically used in order to achieve the required electrical performance and the electromigration behavior as is required in view of reliability of the integrated circuits. Consequently, in lower-lying metallization levels that are positioned above the device contact level, metal lines (M1 and above) and vias (V0 and above) having critical dimensions of approximately 100 nm and significantly less may have to be provided in order to achieve the required packing density in accordance with the density of circuit elements in the device level.
In sophisticated semiconductor devices, tungsten, in combination with appropriate barrier materials, has proven to be a viable contact metal. When forming tungsten-based contact elements, typically, an interlayer dielectric material is formed first and is patterned so as to define contact openings which extend through the interlayer dielectric material to the corresponding contact areas of the circuit elements, i.e., the source/drain region or the gate structure of a transistor.
FIG. 1A is a cross-sectional view of an integrated circuit product 10 comprised of a plurality of transistor devices formed in and above a semiconductor substrate 12. A schematically depicted isolation region 13 has also been formed in the substrate 12. In the depicted example, the transistor devices are comprised of an illustrative gate structure 14, i.e., a gate insulation layer 14A and a gate electrode 14B, a gate cap layer 16, a sidewall spacer 18 and simplistically depicted source/drain regions 20. At the point of fabrication depicted in FIG. 1A, a layer of insulating material 17A, 17B, i.e., the interlayer dielectric, has been formed above the product 10. Other layers of material, such as contact etch stop layers and the like, are not depicted in the attached drawings. Also depicted are illustrative source/drain contact structures 21 which include a combination of a so-called “trench silicide” (TS) structure 22 and a so-called “CA contact” structure 24. Also depicted is a gate contact structure 26 which is sometimes referred to as a “CB contact” structure. The CB contacts 26 are formed so as to contact a portion of the gate electrode 14B of the gate structure 14. In a plan view, the CB contacts 26 are positioned above the isolation region 13, i.e., the CB contacts 26 are not positioned above the active region defined in the substrate 12. The source/drain contact structures 21 are typically formed as line-type structures that extend across the entire width or a significant portion of the active region in the gate-width direction of the transistor devices.
In one embodiment, the process flow of forming the TS structures 22, CA contacts 24 and CB contacts 26 may be as follows. After a first layer of insulating material 17A is deposited, TS openings are formed in the first layer of insulating material 17A that expose portions of underlying source/drain regions 20. Thereafter, traditional silicide is formed through the TS openings followed by forming tungsten (not separately shown) on the metal silicide regions and performing a CMP process down to the top of the gate cap layer 16. Then, a second layer of insulating material 17B is deposited and contact openings for the CA contacts 24 are formed in the second layer of insulating material 17B that expose portions of the underlying tungsten metallization. Next, the opening for the CB contact 26 is formed in the second layer of insulating material 17B and through the gate cap layer 16 so as to expose a portion of the gate electrode 14B. Typically, the CB contact 26 is in the form of a round or square plug. Thereafter, the CA contacts 24 and the CB contact 26 are formed in their corresponding openings in the second layer of insulating material 17B by performing one or more common deposition and CMP process operations, using the second layer of insulating material 17B as a polish-stop layer to remove excess material positioned outside of the contact openings. The CA contacts 24 and CB contact 26 typically contain a uniform body of metal, e.g., tungsten, and may also include one or more metallic barrier layers (not shown) positioned between the uniform body of metal and the layer of insulating material 17B. The source/drain contact structures 21 (TS contacts 22, CA contacts 24) and the CB contact 26 are all considered to be device-level contacts within the industry.
Also depicted in FIG. 1A is the first metallization layer—the so-called M1 layer—of the multi-level metallization system for the product 10. A plurality of conductive vias—so-called V0 vias—are provided to establish electrical connection between the device-level contacts—CA contacts 24 and the CB contact 26—and the M1 layer. The M1 layer typically includes a plurality of metal lines that are routed as needed across the product 10. The M1 lines 30 and the V0 structures are typically comprised of copper, and they are formed in a layer of insulating material 19 using known damascene or dual-damascene techniques. Additional metallization layers (not shown) are formed above the M1 layer, e.g., M2/V1, M3/V2, etc. As depicted, the device-level contacts are all positioned at a level that is below the level of the V0 structures.
FIG. 1B depicts another illustrative arrangement of device-level contacts that may be employed on the product 10. Relative to the example depicted in FIG. 1A, in FIG. 1B, the V0 structures have been omitted and the CA contacts 24 and the CB contact 26 have been extended vertically. In this example, the device-level contacts 24, 26 are all positioned at a level that is below the level of the metal lines in the M1 layer.
FIG. 1C depicts another illustrative arrangement of conductive structures that may be employed on the product 10. In this example, a local interconnect structure 32—a so-called M0 line—is formed in the second layer of insulating material 17B at the same time the CA contacts 24 and the CB contact 26 are formed, and it is formed of the same materials of construction as the CA contacts 24 and the CB contact 26. Use of the local interconnect 32 can be beneficial for several reasons. For example, as depicted in FIG. 1C, due to the presence of the local interconnect 32, the spacing 33 between the V0 vias 28 that are conductively coupled to the CA contacts 24 may be increased, i.e., the left-most V0 via 28 may be shifted to the left due to the existence of the local interconnect 32. In this example, the device-level contacts 21, 26 as well as the local interconnect 32 are all positioned at a level that is below the level of the V0 structures 28.
FIG. 1D is a plan view of a portion of an integrated circuit product that depicts further examples of where a local interconnect structure (M0) may be employed. As shown therein, a first transistor 10A is formed above a first active region (Active 1) while second and third transistors (10B, 10C) are formed above a second active region (Active 2). The spaced-apart active regions are electrically isolated from one another by isolation material (not shown). As depicted therein, line-type CA contacts (CA) are formed above each of the source/drain regions (S/D Region), while CB contacts (CB1-CB3) are formed for each of the gates structures (Gates 1-3). As mentioned previously, the CB contacts are positioned above the isolation material. As depicted, a first local interconnect structure (M0-1) is coupled to a CA contact of transistor 10A and to CB2 contact for Gate 2 of the second transistor 10B. By using the first local interconnect structure (M0-1), the distance 35 between the CB2 contact and the CA contacts on the second transistor 10B may be maintained at an acceptable distance to avoid shorting. A second local interconnect structure (M0-2) is coupled to CB1 contact for Gate 1 of the first transistor 10A and to CB3 contact for Gate 3 of the third transistor 10C. Due to the presence of the second local interconnect structure (M0-2), Gate 1 can be coupled to Gate 3 without shorting to Gate 2.
While all of the various formations of device-level contact structures and local interconnect structures discussed above are possible, another problem that is present with such conductive structures is the overall resistance of the device-level contacts, and particularly the local interconnect structures. The present disclosure is directed to various methods of forming reduced resistance local interconnect structures and the resulting semiconductor devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.